Semiconductor device solderability testing evaluates how reliably the terminations, leads, and solder balls of diodes, transistors, and integrated circuits can be wetted by molten solder to form durable interconnections. This article explains the applicable IEC, ISO, GB, and JIS standards, common sample types, dip-and-look and wetting balance test methods, acceptance criteria, and practical applications of solderability testing performed by accredited third-party laboratories.
Technical Overview
Solderability is the ability of a metal surface—such as a component lead, pad, or solder ball—to be wetted by molten solder under specified conditions of flux, temperature, and time, resulting in a continuous, uniform metallurgical joint. For semiconductor devices, solderability is a critical quality attribute because virtually every discrete device and integrated circuit is ultimately attached to a printed circuit board through a soldering process, whether wave soldering, reflow soldering, or selective soldering.
Solderability testing of semiconductor devices verifies that terminations leaving the manufacturing line, or after a defined period of storage, will form acceptable solder joints in production. Poor solderability manifests as non-wetting, dewetting, pinholes, or exposed base metal, and it directly causes defects such as solder bridging, open joints, insufficient hole fill, and unreliable mechanical and electrical connections. These defects are among the leading drivers of rework cost and field failure in electronics assembly.
The solderability of a semiconductor termination depends on several material and process factors:
- Plating chemistry and thickness, for example matte tin, bright tin, tin-lead, nickel-palladium-gold, or nickel-gold finishes
- Surface cleanliness and the degree of oxidation or contamination on the termination
- Intermetallic compound growth between the plating and the base lead-frame metal over time
- Storage conditions and shelf age, including humidity and temperature exposure
- Consistency of the electroplating or solder-dipping process at the device manufacturer
Because solderability degrades over time, accelerated aging preconditioning—such as steam aging or dry baking—is often applied before the test to simulate end-of-shelf-life conditions and to evaluate the robustness of the plating system.
Testing Samples
Through-Hole Semiconductor Devices
Leaded packages are the classic test subjects for solderability evaluation. Typical samples include small-signal diodes in DO-35 or DO-41 axial formats, power rectifiers, zener diodes, transistors in TO-92 or TO-126 outlines, power MOSFETs and IGBTs in TO-220 or TO-247 packages, thyristors, and dual in-line (DIP) integrated circuits. The tin-plated or solder-dipped leads of these packages are tested after appropriate aging conditioning.
Surface-Mount Semiconductor Devices
Surface-mount packages account for the majority of modern semiconductor devices. Samples include SOT-23 and SOT-223 transistors, SOD-123 and SOD-323 diodes, SOP, SSOP, and TSSOP integrated circuits, QFP and QFN packages with gull-wing or exposed-pad terminations, and BGA packages with attached solder spheres. For BGA devices, the solderability of the balls themselves is assessed using reflow-based evaluation or wetting balance techniques adapted for area-array terminations.
Termination Finishes and Materials
Testing may be performed on the complete finished device or on representative termination samples such as lead-frame strips, plated coupons from the same production lot, or solder preforms and spheres. Common finish systems evaluated include pure matte tin, tin-bismuth, tin-copper and SAC lead-free alloys, Ni/Pd/Au and Ni/Au precious metal systems, and silver finishes. Lead-free finishes require particular attention because of their higher melting ranges and sensitivity to voiding and wetting behavior.
Sample Preparation Requirements
Standards require that samples must not be cleaned, abraded, or otherwise treated before testing, because any such handling would artificially improve wetting performance. Samples must be handled with clean gloves or tweezers to avoid finger contamination. Depending on the specification, samples may be subjected to preconditioning such as steam aging (typically 8 hours) or dry heat baking to simulate long-term storage before the solderability measurement is performed.
Testing Items
A comprehensive solderability evaluation program for semiconductor devices typically includes the following test items:
- Termination solder wettability: qualitative and quantitative assessment of how readily molten solder wets the lead or termination surface
- Solder coverage evaluation: determination of the percentage of the dipped termination area covered by a continuous, smooth new solder coating
- Wetting force measurement: quantitative measurement of the meniscus force between molten solder and the termination using the wetting balance method
- Wetting time measurement: determination of the zero-cross time, which is the time required for the wetting force to change from negative to positive after immersion
- Defect characterization: identification of non-wetting, dewetting, pinholes, voids, exposed base metal, and cold or granular joints
- Aged solderability: solderability assessment after steam aging or baking to verify plating durability at the end of the intended storage life
- Resistance to soldering heat (related item): verification that the device survives soldering temperatures of typically 260 °C for 5 to 10 seconds without electrical or physical damage
These items together provide a complete picture of whether the device will assemble reliably and whether the finish system will remain solderable throughout its specified shelf life.
Testing Methods
Dip-and-Look Solder Bath Method
The dip-and-look method, specified in IEC 60068-2-20 and equivalent national standards such as GB/T 2423.28 and the JIS C 60068 series, is the most widely used qualitative solderability test. The procedure is as follows: the terminations are first fluxed with a defined rosin-based flux, then immersed in a molten solder bath at a controlled temperature—typically 235 °C for tin-lead processes and 245 °C to 250 °C for lead-free processes—for a defined dwell time, commonly 2 to 5 seconds, using a controlled immersion and withdrawal speed. After removal and solidification, the dipped area is examined visually, with magnification where specified, and the solder coverage is estimated.
The standard acceptance criterion requires that at least 95 percent of the critical surface area of the dipped region be covered by a continuous, smooth, and bright new solder coating. Small imperfections such as pinholes or rough spots are acceptable only if they are not concentrated in one area and do not exceed the allowed percentage of the total area, and exposed base metal is generally not acceptable.
Wetting Balance Method
The wetting balance method, covered by IEC 60068-2-54, IEC 60068-2-58, and IEC 60068-2-69, provides a quantitative and objective record of the soldering behavior of a termination. The sample is clamped to a sensitive force-measuring transducer and immersed vertically into the molten solder bath through an angle-matched gauge. As the solder wets the termination, the instrument records the net vertical force as a function of time.
The resulting force–time curve yields two principal parameters: the zero-cross time, which is the moment the buoyancy-dominated negative force becomes positive as true wetting begins, and the wetting force achieved at a defined evaluation time, typically 2 seconds, expressed in micronewtons per millimeter of termination perimeter. Acceptance criteria in most specifications require the zero-cross time to fall below a maximum limit, commonly 1 to 2 seconds, and the wetting force to exceed a minimum value defined as a percentage of the theoretical meniscus force for the geometry. Because the output is numerical, the wetting balance is particularly valuable for comparing plating lots, tracking solderability degradation over storage time, and supporting statistical process control.
Solder Globule Method
For round or rectangular leads where full immersion is impractical, the solder globule method places a defined small volume of molten solder in contact with the termination and evaluates the time required for the solder to spread and envelope the specified contact length. This technique, included within the IEC 60068-2-20 family of procedures, is useful for axial lead components and fine-pitch leads.
Preconditioning and Aging Treatments
Before solderability assessment, samples may be subjected to steam aging—typically 8 hours of exposure to saturated steam—or dry heat conditioning in an oven to accelerate oxidation and intermetallic growth. This simulates the natural degradation expected during storage and allows the laboratory to classify device finishes according to their expected solderable life. Evaluation both in the as-received condition and after aging provides a complete picture of plating robustness.
Standards Framework
The primary reference standards for semiconductor device solderability testing include the IEC 60068-2 series for environmental testing (dip, globule, and wetting balance methods), the IEC 60749 series for mechanical and climatic test methods specific to semiconductor devices, and their national adoptions such as the GB/T 4937 series and GB/T 2423.28. Test method consistency is further supported by ISO and ASTM guidance on solderability and surface finish evaluation. Accredited third-party laboratories select the applicable method and conditions based on the device package style, termination finish, and the customer's product specification or purchase agreement.
Applications
Semiconductor device solderability testing is applied throughout the electronics supply chain, from component fabrication to board assembly and failure analysis. Typical application scenarios include:
- Incoming quality control of purchased semiconductor components before they are committed to production lines
- Qualification of new package designs, lead-frame materials, and plating chemistries prior to mass production release
- Validation after process changes at the plating line, such as changes in plating thickness, bath chemistry, or solder-dipping parameters
- Shelf-life studies and storage durability assessment for components held in inventory for extended periods
- Lead-free transition programs, verifying that matte tin and SAC-alloy finishes meet wetting criteria at lead-free processing temperatures
- Root-cause failure analysis when assembly lines experience non-wetting, dewetting, tombstoning, or insufficient solder fillets
- Supplier qualification audits and lot acceptance testing performed by accredited third-party laboratories under customer or industry specifications
Industries that depend on this testing include consumer electronics, telecommunications, automotive electronics, industrial controls, medical devices, and aerospace systems, where solder joint integrity is essential to long-term product reliability and safety.
FAQ
What is semiconductor device solderability testing?
It is a laboratory evaluation that determines whether the terminations of a semiconductor device—leads, pads, or solder balls—can be properly wetted by molten solder under standardized flux, temperature, and time conditions. The test predicts whether the device will form reliable solder joints during printed circuit board assembly.
Which standards govern the test?
The most commonly applied standards are IEC 60068-2-20 for dip and globule methods, IEC 60068-2-54 and IEC 60068-2-69 for wetting balance methods, IEC 60068-2-58 for surface-mount devices, and the IEC 60749 series for semiconductor devices specifically. In China, the corresponding GB/T 4937 and GB/T 2423.28 standards are widely used, and JIS C 60068 series standards apply in the Japanese market.
What is the difference between dip-and-look and wetting balance testing?
Dip-and-look is a qualitative pass/fail method in which the termination is dipped in molten solder and visually judged against a minimum 95 percent coverage criterion. The wetting balance is a quantitative method that records wetting force versus immersion time, producing measurable parameters such as zero-cross time and wetting force, which allow objective comparison between lots and finishes.
Why is steam aging performed before the test?
Steam aging accelerates oxidation and intermetallic growth on the termination surface, simulating the degradation that occurs during long-term storage. Testing after aging verifies that the finish will still be solderable near the end of its specified shelf life, not only when freshly manufactured.
How are lead-free devices tested differently?
Lead-free finishes such as matte tin or SAC alloys are tested using lead-free solder bath temperatures, typically 245 °C to 250 °C, and evaluation criteria adapted for the higher melting range. The test also helps confirm the finish quality that influences tin whisker mitigation and reflow window compatibility.
How many samples are required?
The required sample quantity depends on the governing specification, package type, and whether testing is performed in the as-received condition, after aging, or both. Accredited third-party laboratories typically recommend a statistically meaningful sample from each plating lot or shipment, and customers should confirm the sampling plan with the laboratory before testing begins.